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MTRR-WC enabler for VESA LFB 1.6 (C) 2005-2021 by Martin Rehak; rayer@seznam.cz
Compiled by GCC 4.8.5 at 06:20:59, Mar 11 2021
Host machine CPU vendor: GenuineIntel, ID: 306C3h
VESA 3.0 NVIDIA [262144 kB]
NVIDIA Corporation
G71 Board - p455h7s
Chip Rev
LFB address: E0000000h
MTRR #0: base = 000000000h ( 0MB), mask = F80000000h ( 2048MB), WB, used
MTRR #1: base = 080000000h ( 2048MB), mask = FC0000000h ( 1024MB), WB, used
MTRR #2: base = 0E0000000h ( 3584MB), mask = FF0000000h ( 256MB), WC, used
MTRR #3: base = 200000000h ( 8192MB), mask = FF0000000h ( 256MB), WB, used
MTRR #4: base = 210000000h ( 8448MB), mask = FF8000000h ( 128MB), WB, used
MTRR #5: base = 218000000h ( 8576MB), mask = FFC000000h ( 64MB), WB, used
MTRR #6: base = 21C000000h ( 8640MB), mask = FFE000000h ( 32MB), WB, used
MTRR #7: base = 21E000000h ( 8672MB), mask = FFF000000h ( 16MB), WB, used
MTRR #8: base = 000000000h ( 0MB), mask = 000000000h ( 0MB), UC, unused
MTRR #9: base = 000000000h ( 0MB), mask = 000000000h ( 0MB), UC, unused |
Всего записей: 757 | Зарегистр. 05-08-2011 | Отправлено: 18:10 14-06-2022 | Исправлено: logins, 20:15 14-06-2022 |
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